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Added bitfieldInterleave implementation

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This commit is contained in:
Christophe Riccio
2013-02-01 23:55:25 +01:00
parent df0d9e687e
commit c57a000791
5 changed files with 524 additions and 339 deletions
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50
glm/core/intrinsic_integer.hpp Normal file
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@@ -0,0 +1,50 @@
///////////////////////////////////////////////////////////////////////////////////
/// OpenGL Mathematics (glm.g-truc.net)
///
/// Copyright (c) 2005 - 2012 G-Truc Creation (www.g-truc.net)
/// Permission is hereby granted, free of charge, to any person obtaining a copy
/// of this software and associated documentation files (the "Software"), to deal
/// in the Software without restriction, including without limitation the rights
/// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
/// copies of the Software, and to permit persons to whom the Software is
/// furnished to do so, subject to the following conditions:
///
/// The above copyright notice and this permission notice shall be included in
/// all copies or substantial portions of the Software.
///
/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
/// THE SOFTWARE.
///
/// @ref core
/// @file glm/core/intrinsic_integer.hpp
/// @date 2009-05-11 / 2011-06-15
/// @author Christophe Riccio
///////////////////////////////////////////////////////////////////////////////////
#ifndef glm_detail_intrinsic_integer
#define glm_detail_intrinsic_integer
#include "setup.hpp"
#if(!(GLM_ARCH & GLM_ARCH_SSE2))
# error "SSE2 instructions not supported or enabled"
#else
namespace glm{
namespace detail
{
__m128i _mm_bit_interleave_si128(__m128i x)
__m128i _mm_bit_interleave_si128(__m128i x, __m128i y);
}//namespace detail
}//namespace glm
#include "intrinsic_integer.inl"
#endif//GLM_ARCH
#endif//glm_detail_intrinsic_integer

140
glm/core/intrinsic_integer.inl Normal file
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///////////////////////////////////////////////////////////////////////////////////
/// OpenGL Mathematics (glm.g-truc.net)
///
/// Copyright (c) 2005 - 2012 G-Truc Creation (www.g-truc.net)
/// Permission is hereby granted, free of charge, to any person obtaining a copy
/// of this software and associated documentation files (the "Software"), to deal
/// in the Software without restriction, including without limitation the rights
/// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
/// copies of the Software, and to permit persons to whom the Software is
/// furnished to do so, subject to the following conditions:
///
/// The above copyright notice and this permission notice shall be included in
/// all copies or substantial portions of the Software.
///
/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
/// THE SOFTWARE.
///
/// @ref core
/// @file glm/core/intrinsic_integer.inl
/// @date 2009-05-08 / 2011-06-15
/// @author Christophe Riccio
///////////////////////////////////////////////////////////////////////////////////
namespace glm{
namespace detail
{
inline __m128i _mm_bit_interleave_si128(__m128i x)
{
__m128i const Mask4 = _mm_set1_epi32(0x0000FFFF);
__m128i const Mask3 = _mm_set1_epi32(0x00FF00FF);
__m128i const Mask2 = _mm_set1_epi32(0x0F0F0F0F);
__m128i const Mask1 = _mm_set1_epi32(0x33333333);
__m128i const Mask0 = _mm_set1_epi32(0x55555555);
__m128i Reg1;
__m128i Reg2;
// REG1 = x;
// REG2 = y;
//Reg1 = _mm_unpacklo_epi64(x, y);
Reg1 = x;
//REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x0000FFFF0000FFFF);
//REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFF);
Reg2 = _mm_slli_si128(Reg1, 2);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask4);
//REG1 = ((REG1 << 8) | REG1) & glm::uint64(0x00FF00FF00FF00FF);
//REG2 = ((REG2 << 8) | REG2) & glm::uint64(0x00FF00FF00FF00FF);
Reg2 = _mm_slli_si128(Reg1, 1);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask3);
//REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x0F0F0F0F0F0F0F0F);
//REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x0F0F0F0F0F0F0F0F);
Reg2 = _mm_slli_epi32(Reg1, 4);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask2);
//REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x3333333333333333);
//REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x3333333333333333);
Reg2 = _mm_slli_epi32(Reg1, 2);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask1);
//REG1 = ((REG1 << 1) | REG1) & glm::uint64(0x5555555555555555);
//REG2 = ((REG2 << 1) | REG2) & glm::uint64(0x5555555555555555);
Reg2 = _mm_slli_epi32(Reg1, 1);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask0);
//return REG1 | (REG2 << 1);
Reg2 = _mm_slli_epi32(Reg1, 1);
Reg2 = _mm_srli_si128(Reg2, 8);
Reg1 = _mm_or_si128(Reg1, Reg2);
return Reg1;
}
inline __m128i _mm_bit_interleave_si128(__m128i x, __m128i y)
{
__m128i const Mask4 = _mm_set1_epi32(0x0000FFFF);
__m128i const Mask3 = _mm_set1_epi32(0x00FF00FF);
__m128i const Mask2 = _mm_set1_epi32(0x0F0F0F0F);
__m128i const Mask1 = _mm_set1_epi32(0x33333333);
__m128i const Mask0 = _mm_set1_epi32(0x55555555);
__m128i Reg1;
__m128i Reg2;
// REG1 = x;
// REG2 = y;
Reg1 = _mm_unpacklo_epi64(x, y);
//REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x0000FFFF0000FFFF);
//REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFF);
Reg2 = _mm_slli_si128(Reg1, 2);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask4);
//REG1 = ((REG1 << 8) | REG1) & glm::uint64(0x00FF00FF00FF00FF);
//REG2 = ((REG2 << 8) | REG2) & glm::uint64(0x00FF00FF00FF00FF);
Reg2 = _mm_slli_si128(Reg1, 1);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask3);
//REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x0F0F0F0F0F0F0F0F);
//REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x0F0F0F0F0F0F0F0F);
Reg2 = _mm_slli_epi32(Reg1, 4);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask2);
//REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x3333333333333333);
//REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x3333333333333333);
Reg2 = _mm_slli_epi32(Reg1, 2);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask1);
//REG1 = ((REG1 << 1) | REG1) & glm::uint64(0x5555555555555555);
//REG2 = ((REG2 << 1) | REG2) & glm::uint64(0x5555555555555555);
Reg2 = _mm_slli_epi32(Reg1, 1);
Reg1 = _mm_or_si128(Reg2, Reg1);
Reg1 = _mm_and_si128(Reg1, Mask0);
//return REG1 | (REG2 << 1);
Reg2 = _mm_slli_epi32(Reg1, 1);
Reg2 = _mm_srli_si128(Reg2, 8);
Reg1 = _mm_or_si128(Reg1, Reg2);
return Reg1;
}
}//namespace detail
}//namespace glms

117
glm/gtx/bit.inl
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@@ -608,11 +608,90 @@ namespace glm
Result |= (x & 1U << i) << i | (y & 1U << i) << (i + 1);
return Result;
}
template <>
inline glm::uint16 bitfieldInterleave(glm::uint8 x, glm::uint8 y)
{
glm::uint16 REG1(x);
glm::uint16 REG2(y);
REG1 = ((REG1 << 4) | REG1) & glm::uint16(0x0F0F);
REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F);
REG1 = ((REG1 << 2) | REG1) & glm::uint16(0x3333);
REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333);
REG1 = ((REG1 << 1) | REG1) & glm::uint16(0x5555);
REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555);
return REG1 | (REG2 << 1);
}
template <>
inline glm::uint32 bitfieldInterleave(glm::uint16 x, glm::uint16 y)
{
glm::uint32 REG1(x);
glm::uint32 REG2(y);
REG1 = ((REG1 << 8) | REG1) & glm::uint32(0x00FF00FF);
REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF);
REG1 = ((REG1 << 4) | REG1) & glm::uint32(0x0F0F0F0F);
REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F);
REG1 = ((REG1 << 2) | REG1) & glm::uint32(0x33333333);
REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333);
REG1 = ((REG1 << 1) | REG1) & glm::uint32(0x55555555);
REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555);
return REG1 | (REG2 << 1);
}
template <>
inline glm::uint64 bitfieldInterleave(glm::uint32 x, glm::uint32 y)
{
glm::uint64 REG1(x);
glm::uint64 REG2(y);
REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x0000FFFF0000FFFF);
REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFF);
REG1 = ((REG1 << 8) | REG1) & glm::uint64(0x00FF00FF00FF00FF);
REG2 = ((REG2 << 8) | REG2) & glm::uint64(0x00FF00FF00FF00FF);
REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x0F0F0F0F0F0F0F0F);
REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x0F0F0F0F0F0F0F0F);
REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x3333333333333333);
REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x3333333333333333);
REG1 = ((REG1 << 1) | REG1) & glm::uint64(0x5555555555555555);
REG2 = ((REG2 << 1) | REG2) & glm::uint64(0x5555555555555555);
return REG1 | (REG2 << 1);
}
}//namespace detail
inline int16 bitfieldInterleave(int8 x, int8 y)
{
return detail::bitfieldInterleave<int8, int16>(x, y);
union sign8
{
int8 i;
uint8 u;
} sign_x, sign_y;
union sign16
{
int16 i;
uint16 u;
} result;
sign_x.i = x;
sign_y.i = y;
result.u = detail::bitfieldInterleave<int8, int16>(sign_x.u, sign_y.u);
return result.i;
}
inline uint16 bitfieldInterleave(uint8 x, uint8 y)
@@ -622,7 +701,23 @@ namespace glm
inline int32 bitfieldInterleave(int16 x, int16 y)
{
return detail::bitfieldInterleave<int16, int32>(x, y);
union sign16
{
int16 i;
uint16 u;
} sign_x, sign_y;
union sign32
{
int32 i;
uint32 u;
} result;
sign_x.i = x;
sign_y.i = y;
result.u = detail::bitfieldInterleave<int16, int32>(sign_x.u, sign_y.u);
return result.i;
}
inline uint32 bitfieldInterleave(uint16 x, uint16 y)
@@ -632,7 +727,23 @@ namespace glm
inline int64 bitfieldInterleave(int32 x, int32 y)
{
return detail::bitfieldInterleave<int32, int64>(x, y);
union sign32
{
int32 i;
uint32 u;
} sign_x, sign_y;
union sign64
{
int64 i;
uint64 u;
} result;
sign_x.i = x;
sign_y.i = y;
result.u = detail::bitfieldInterleave<int32, int64>(sign_x.u, sign_y.u);
return result.i;
}
inline uint64 bitfieldInterleave(uint32 x, uint32 y)