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860 Commits

Author SHA1 Message Date
Christophe Riccio
c5f48da319 Fixed build with compiler that doesn't support GLM_HAS_UNRESTRICTED_UNIONS 2016-05-28 00:10:18 +02:00
Christophe Riccio
ae6082db5e Added AVX2 bitwise optimization 2016-05-28 00:00:33 +02:00
Christophe Riccio
f577611328 Added bitwise inverse SIMD optimization. Factorized bitwise optimization code 2016-05-27 23:03:38 +02:00
Christophe Riccio
4797ea9540 Added specialized SSE2 and AVX bool mix 2016-05-26 02:47:43 +02:00
Christophe Riccio
72c741d8ea Fixed sign with signed integer function on non-x86 architecture 2016-05-24 13:29:18 +02:00
Christophe Riccio
1208eb63f7 Added NEON, MIPS and PowerPC detection 2016-05-23 23:35:34 +02:00
Christophe Riccio
316460408a Simplify and more consistency for files headers 2016-05-23 22:55:49 +02:00
Christophe Riccio
62d5e0ce45 Fixed build 2016-05-23 21:59:25 +02:00
Christophe Riccio
8b9d205178 Fixed build 2016-05-23 21:57:26 +02:00
Christophe Riccio
3f74efa2e0 Merge simd branch 2016-05-23 21:52:59 +02:00
Christophe Riccio
b87ead8304 Use unary bit operators for binary implementation 2016-05-23 21:47:35 +02:00
Christophe Riccio
3081b44ed2 Use unary bit operators for binary implementation 2016-05-23 21:45:08 +02:00
Christophe Riccio
d871d753dc Use unary bit operators for binary implementation 2016-05-23 21:39:33 +02:00
Christophe Riccio
5e60c54004 Use unary % operator for binary implementation 2016-05-23 21:24:59 +02:00
Christophe Riccio
eab004bfe5 vec4 add, sub, mul and div binary operators use unary operators implementation 2016-05-23 21:20:04 +02:00
Christophe Riccio
276505f409 add, sub, mul and div vec4 for specialization 2016-05-23 21:13:57 +02:00
Christophe Riccio
c0fc71803c Integer SSE code generation 2016-05-23 01:54:55 +02:00
Christophe Riccio
ff74b87b48 Generate SSE instructions for sub, mul and div including lowp div 2016-05-23 00:34:59 +02:00
Christophe Riccio
0e780a5efd - Use Cuda built-in function for abs function implementation with Cuda compiler 2016-05-22 18:04:32 +02:00
Christophe Riccio
cc9916b2c6 Fixed build, missing reference to inverse function 2016-05-22 17:28:18 +02:00
Christophe Riccio
757fe39587 Removed simd precision qualifier. All precision qualifiers may generate SIMD instructions, precision may affect the generated instructions accordingly 2016-05-22 17:12:32 +02:00
Christophe Riccio
93a2f03649 Merge branch '0.9.7' 2016-05-18 22:53:00 +02:00
Christophe Riccio
dcffcbdc97 Fixed GLM_FORCE_INLINE with binary vec4 operators 2016-05-18 22:52:47 +02:00
Christophe Riccio
fd06877778 Too big bug with GCC 4.6 constexpr, haven't tried 4.7, let's see how 4.8 does 2016-05-05 21:06:27 +02:00
Christophe Riccio
60a5f4aea9 Too big bug with GCC 4.6 constexpr, haven't tried 4.7, let's see how 4.8 does 2016-05-05 20:57:37 +02:00
Christophe Riccio
a6047251be Fixed constexpr with SIMD interaction 2016-05-05 20:43:09 +02:00
Christophe Riccio
92a46735d6 Workaround GCC compiler bug with constexpr support 2016-05-05 20:05:31 +02:00
Christophe Riccio
71401d14aa Workaround GCC compiler bug with constexpr support 2016-05-05 19:58:12 +02:00
Christophe Riccio
152c71abff Workaround GCC compiler bug with constexpr support 2016-05-05 19:47:42 +02:00
Christophe Riccio
6d302792ab - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 15:06:03 +02:00
Christophe Riccio
d52766297d - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 14:13:21 +02:00
Christophe Riccio
33bc27ddc4 - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 14:03:20 +02:00
Christophe Riccio
3df1c8755c - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 13:56:40 +02:00
Christophe Riccio
c50f3ed38e - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 13:40:11 +02:00
Christophe Riccio
d0c4bbaef7 - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 13:27:26 +02:00
Christophe Riccio
9a7b802bdc - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 13:05:15 +02:00
Christophe Riccio
7193cd2c3a - Added constexpr for *vec*, *mat*, *quat* and *dual_quat* types #493 2016-05-05 10:38:51 +02:00
Christophe Riccio
93612791cd Removed Apple specific check for LLVM versions 2016-05-04 18:46:59 +02:00
Christophe Riccio
20da5a25db Improved OpenMP support detection for Clang, GCC, ICC and VC 2016-05-04 18:04:44 +02:00
Christophe Riccio
ca3abd6e93 Fixed CUDA support #499, #500, #501 2016-05-04 17:05:02 +02:00
Christophe Riccio
13a997d4e1 Fixed CUDA support #499, #500, #501 2016-05-04 17:03:38 +02:00
Christophe Riccio
affd5f3ba0 Fixed CUDA compiler error in type_vec4.inl #504 2016-05-04 16:35:57 +02:00
Christophe Riccio
1f71f6fb3a Improved SIMD and swizzle operators interactions with GCC and Clang, Added raw SIMD API. 2016-05-03 23:57:41 +02:00
Christophe Riccio
1becd76c5f Fixed build 2016-05-01 12:39:16 +02:00
Christophe Riccio
83999c749a Reorganized SIMD code 2016-05-01 12:29:11 +02:00
Christophe Riccio
96963f88cc Single file for simd specialization 2016-05-01 05:00:13 +02:00
Christophe Riccio
5f05a5e953 Clean up inverse SSE code 2016-05-01 03:42:47 +02:00
Christophe Riccio
a90ef1b45e Fixed warning 2016-05-01 01:31:43 +02:00
Christophe Riccio
b53cc5d098 Fixed build on non-VC compilers 2016-05-01 01:26:42 +02:00
Christophe Riccio
2f9fc55d88 More experiments to improve SIMD support 2016-05-01 01:12:22 +02:00