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Add bit width of types to disassembleInstruction

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This commit is contained in:
Jeff Bolz
2018-05-22 23:13:30 -05:00
parent c6d255396f
commit af7a94876c
43 changed files with 7980 additions and 7959 deletions
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27
SPIRV/disassemble.cpp Normal file → Executable file
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@@ -353,10 +353,21 @@ void SpirvStream::disassembleInstruction(Id resultId, Id /*typeId*/, Op opCode,
if (resultId != 0 && idDescriptor[resultId].size() == 0) {
switch (opCode) {
case OpTypeInt:
idDescriptor[resultId] = "int";
switch (stream[word]) {
case 8: idDescriptor[resultId] = "int8_t"; break;
case 16: idDescriptor[resultId] = "int16_t"; break;
default: assert(0); // fallthrough
case 32: idDescriptor[resultId] = "int"; break;
case 64: idDescriptor[resultId] = "int64_t"; break;
}
break;
case OpTypeFloat:
idDescriptor[resultId] = "float";
switch (stream[word]) {
case 16: idDescriptor[resultId] = "float16_t"; break;
default: assert(0); // fallthrough
case 32: idDescriptor[resultId] = "float"; break;
case 64: idDescriptor[resultId] = "float64_t"; break;
}
break;
case OpTypeBool:
idDescriptor[resultId] = "bool";
@@ -368,8 +379,18 @@ void SpirvStream::disassembleInstruction(Id resultId, Id /*typeId*/, Op opCode,
idDescriptor[resultId] = "ptr";
break;
case OpTypeVector:
if (idDescriptor[stream[word]].size() > 0)
if (idDescriptor[stream[word]].size() > 0) {
idDescriptor[resultId].append(idDescriptor[stream[word]].begin(), idDescriptor[stream[word]].begin() + 1);
if (strstr(idDescriptor[stream[word]].c_str(), "8")) {
idDescriptor[resultId].append("8");
}
if (strstr(idDescriptor[stream[word]].c_str(), "16")) {
idDescriptor[resultId].append("16");
}
if (strstr(idDescriptor[stream[word]].c_str(), "64")) {
idDescriptor[resultId].append("64");
}
}
idDescriptor[resultId].append("vec");
switch (stream[word + 1]) {
case 2: idDescriptor[resultId].append("2"); break;