WIP: HLSL: hlsl register class iomapping

Adds --hlsl-iomap option to perform IO mapping in HLSL register space.

--shift-cbuffer-binding is now a synonym for --shift-ubo-binding.

The idea way to do this seems to be passing in a dedicated IO resolver, but
that would require more intrusive restructuring, so maybe best for its
own PR.

The TDefaultHlslIoResolver class and the former TDefaultIoResolver class
share quite a bit of mechanism in a common base class.

TODO: tbuffers are landing in the wrong register class, which needs some
investigation.  They're either wrong upstream, or the detection in the
resolver is wrong.

Test/baseResults/hlsl.automap.frag.out

@@ -0,0 +1,27 @@
+hlsl.automap.frag
+Uniform reflection:
+t1: offset -1, type 8b5d, size 1, index -1, binding 11
+t2: offset -1, type 8b5e, size 1, index -1, binding 12
+t3: offset -1, type 8b5f, size 1, index -1, binding 13
+t4.@data: offset 0, type 8b52, size 1, index 0, binding -1
+t5.@data: offset 0, type 1405, size 0, index 1, binding -1
+t6: offset -1, type 8dc2, size 1, index -1, binding 16
+s1: offset -1, type 0, size 1, index -1, binding 31
+s2: offset -1, type 0, size 1, index -1, binding 32
+u1: offset -1, type 904c, size 1, index -1, binding 41
+u2: offset -1, type 904d, size 1, index -1, binding 42
+u3: offset -1, type 904e, size 1, index -1, binding 43
+u4: offset -1, type 9051, size 1, index -1, binding 44
+u5.@data: offset 0, type 1405, size 0, index 2, binding -1
+u6.@data: offset 0, type 1406, size 1, index 3, binding -1
+cb1: offset 0, type 1404, size 1, index 4, binding -1
+
+Uniform block reflection:
+t4: offset -1, type ffffffff, size 0, index -1, binding 14
+t5: offset -1, type ffffffff, size 0, index -1, binding 15
+u5: offset -1, type ffffffff, size 0, index -1, binding 45
+u6: offset -1, type ffffffff, size 0, index -1, binding 46
+cb: offset -1, type ffffffff, size 4, index -1, binding 51
+
+Vertex attribute reflection:
+