John Kessenich
d6c975572e
Change the major revision number for next commit.
2018-06-04 15:33:31 -06:00
John Kessenich
ac3707921e
Revert the commits that change OpArrayLength type and bumped the version number.
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Now, version 5.* is all connected to making the uint type, which doesn't quite work.
Generator versions 4 and 6 do not do this.
2018-03-07 11:48:25 -07:00
John Kessenich
0216f24f0e
SPV: Bump up the generator number.
2018-03-03 11:47:07 -07:00
John Kessenich
71b5da60d0
SPV: Bump up generator number, because previous commit changes code gen slightly.
2018-02-06 08:06:36 -07:00
John Kessenich
2b5ea9f851
SPV Version: Emit the requested SPIR-V version, not the header version.
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Fixes #1236 .
2018-01-31 18:41:59 -07:00
John Kessenich
6c1c2766b6
SPV: Bump SPIR-V header to the unified1 version (version 1.2).
2018-01-29 16:16:11 -07:00
John Kessenich
c72e5937dd
SPV: Bump the generator number to account for barrier changes.
2017-12-16 00:34:08 -07:00
John Kessenich
07ed11f9a0
SPV: GeneratorVersion: bump version number because of atomic decrement change.
2017-10-07 11:41:20 -06:00
John Kessenich
4baebea8d6
HLSL Test: Expand test, adding a user-patch-constant signature.
2017-08-10 11:41:11 -06:00
John Kessenich
e516d4335f
HLSL: Move debug naming to a simpler, more consistent, scheme.
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This will help in expanding flattening and reducing splitting.
2017-08-09 14:29:29 -06:00
John Kessenich
b6be80f44e
HLSL: Flatten more I/O: non-arrayed user-only structures.
...
The goal is to flatten all I/O, but there are multiple categories and
steps to complete, likely including a final unification of splitting
and flattening.
2017-08-04 12:19:58 -06:00
John Kessenich
cca42a8ea6
HLSL: Stop including empty structures in the I/O interface. Fix #785 .
2017-08-03 18:41:48 -06:00
John Kessenich
6fa17641b5
HLSL: Emit the OpSource HLSL instruction for HLSL, using new headers.
2017-04-07 15:40:01 -06:00
steve-lunarg
e741249b72
HLSL: pass tessellation execution modes through to SPIR-V
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The SPIR-V generator had assumed tessellation modes such as
primitive type and vertex order would only appear in tess eval
(domain) shaders. SPIR-V allows either, and HLSL allows and
possibly requires them to be in the hull shader.
This change:
1. Passes them through for either tessellation stage, and,
2. Does not set up defaults in the domain stage for HLSl compilation,
to avoid conflicting definitions.
2017-03-31 11:47:18 -06:00