Specifically, add flattening of arrayed io for geometry and
tesselation shaders. Previously some interface structs just had
builtins split out which caused some interfaces to not be exactly
the same as that of flattened adjacent stages, affecting validation
and correctness.
This obviates builtin splitting. That will be removed in a followup
commit. It was left in for this commit to better exhibit the functional
changes that were made.
Fixes#1660.
The goal is to flatten all I/O, but there are multiple categories and
steps to complete, likely including a final unification of splitting
and flattening.
The SPIR-V generator had assumed tessellation modes such as
primitive type and vertex order would only appear in tess eval
(domain) shaders. SPIR-V allows either, and HLSL allows and
possibly requires them to be in the hull shader.
This change:
1. Passes them through for either tessellation stage, and,
2. Does not set up defaults in the domain stage for HLSl compilation,
to avoid conflicting definitions.
