Filip Wasil
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4266c75f40
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riscv: Remove unused argument
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-06-28 16:19:11 +03:00 |
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Filip Wasil
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f451a4de09
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riscv: Simplify the runtime check to always be present
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-06-28 16:19:11 +03:00 |
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Filip Wasil
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0e37c0b477
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riscv: Fix more comments
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-05-14 22:35:47 +03:00 |
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Filip Wasil
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7108843467
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riscv: Fix the run-time checking of the RVV availability
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-05-14 10:24:58 +03:00 |
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Filip Wasil
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2b0eb78656
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riscv: Fix autotools definitions and comments
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-05-14 10:24:58 +03:00 |
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Filip Wasil
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ffb8e8b26f
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Fix and improve the RISC-V Vector (RVV) implementation
Changes include manually merged code from Manfred SCHLAEGL.
Co-authored-by: Manfred SCHLAEGL <manfred.schlaegl@gmx.at>
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-05-01 17:44:00 +03:00 |
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Dragoș Tiselice
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cc5ee6b213
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Add optimized RISC-V Vector functions
Largely based off of the ARM NEON implementation.
Signed-off-by: Cosmin Truta <ctruta@gmail.com>
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2025-05-01 17:44:00 +03:00 |
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