mirror of
https://git.code.sf.net/p/libpng/code.git
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a7fe3414e5
Completion of this port required a rerun of `./autogen.sh --maintainer` followed by a rebuild of scripts/pnglibconf.h.prebuilt.
143 lines
3.8 KiB
C
143 lines
3.8 KiB
C
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/* contrib/mips-mmi/linux.c
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*
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* Copyright (c) 2024 Cosmin Truta
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* Written by guxiwei, 2023
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*
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* This code is released under the libpng license.
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* For conditions of distribution and use, see the disclaimer
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* and license in png.h
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/auxv.h>
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/*
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* parse_r var, r - Helper assembler macro for parsing register names.
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*
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* This converts the register name in $n form provided in \r to the
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* corresponding register number, which is assigned to the variable \var. It is
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* needed to allow explicit encoding of instructions in inline assembly where
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* registers are chosen by the compiler in $n form, allowing us to avoid using
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* fixed register numbers.
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*
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* It also allows newer instructions (not implemented by the assembler) to be
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* transparently implemented using assembler macros, instead of needing separate
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* cases depending on toolchain support.
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*
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* Simple usage example:
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* __asm__ __volatile__("parse_r __rt, %0\n\t"
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* ".insn\n\t"
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* "# di %0\n\t"
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* ".word (0x41606000 | (__rt << 16))"
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* : "=r" (status);
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*/
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/* Match an individual register number and assign to \var */
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#define _IFC_REG(n) \
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".ifc \\r, $" #n "\n\t" \
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"\\var = " #n "\n\t" \
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".endif\n\t"
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__asm__(".macro parse_r var r\n\t"
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"\\var = -1\n\t"
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_IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
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_IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
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_IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
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_IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
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_IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
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_IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
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_IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
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_IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
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".iflt \\var\n\t"
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".error \"Unable to parse register name \\r\"\n\t"
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".endif\n\t"
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".endm");
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#define HWCAP_LOONGSON_CPUCFG (1 << 14)
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static int cpucfg_available(void)
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{
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return getauxval(AT_HWCAP) & HWCAP_LOONGSON_CPUCFG;
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}
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static int strstart(const char *str, const char *pfx, const char **ptr)
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{
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while (*pfx && *pfx == *str) {
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pfx++;
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str++;
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}
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if (!*pfx && ptr)
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*ptr = str;
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return !*pfx;
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}
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/* Most toolchains have no CPUCFG support yet */
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static uint32_t read_cpucfg(uint32_t reg)
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{
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uint32_t __res;
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__asm__ __volatile__(
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"parse_r __res,%0\n\t"
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"parse_r reg,%1\n\t"
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".insn \n\t"
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".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
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:"=r"(__res)
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:"r"(reg)
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:
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);
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return __res;
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}
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#define LOONGSON_CFG1 0x1
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#define LOONGSON_CFG1_MMI (1 << 4)
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static int cpu_flags_cpucfg(void)
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{
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int flags = 0;
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uint32_t cfg1 = read_cpucfg(LOONGSON_CFG1);
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if (cfg1 & LOONGSON_CFG1_MMI)
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flags = 1;
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return flags;
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}
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static int cpu_flags_cpuinfo(void)
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{
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FILE *f = fopen("/proc/cpuinfo", "r");
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char buf[200];
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int flags = 0;
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if (!f)
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return flags;
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while (fgets(buf, sizeof(buf), f)) {
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/* Legacy kernel may not export MMI in ASEs implemented */
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if (strstart(buf, "cpu model", NULL)) {
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if (strstr(buf, "Loongson-3 "))
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flags = 1;
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break;
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}
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if (strstart(buf, "ASEs implemented", NULL)) {
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if (strstr(buf, " loongson-mmi"))
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flags = 1;
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break;
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}
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}
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fclose(f);
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return flags;
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}
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static int png_have_mmi()
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{
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if (cpucfg_available())
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return cpu_flags_cpucfg();
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else
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return cpu_flags_cpuinfo();
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return 0;
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}
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